5.19 DTR Fast Read (DTR_FR)

The DTR Fast Read (DTR_FR) instruction is initiated by issuing the 8-bit command 0DH in SPI mode. After the command is received, the device switches to dual data rate (DTR) operation to accept a 3‑byte address, followed by the required dummy clock cycles. The number of dummy clocks depends on the operating frequency, as defined in Table 5-8. The appropriate dummy clock settings must be written to Status Register 3, bits [1:0], prior to issuing this command. The CE# must remain active-low for the entire duration of the DTR Fast Read operation (see Figure 5-17 for the DTR Fast Read sequence).

After the dummy cycles, the device outputs data on SIO1/SO using dual data rate, starting from the specified address. Data are continuously streamed across sequential addresses until the operation is terminated by a low‑to‑high transition on CE#. The internal Address Pointer automatically increments and, upon reaching the highest memory address, wraps around to the beginning of the address space.

In QPI mode, the host initiates the operation by asserting CE# low and issuing the Read command (0DH). The device then switches to dual data rate operation for the 3‑byte address phase, followed by dummy clocks configured by the Set Read Parameters (COH) instruction, as described in Table 5-13. The required number of dummy clocks varies with the operating frequency. Refer to Figure 5-18 for the DTR Fast Read sequence in QPI mode. After the dummy cycles, the device outputs data on SIO[3:0] on the falling edge of the SCK signal, starting from the specified address.