5.50 Write Disable (WRDI)

The Write Disable (WRDI) instruction sets the Write Enable Latch bit in Status Register 1 to 0, thereby preventing write operations. The WRDI instruction is ignored while an internal write operation is in progress, and any write operation initiated prior to executing WRDI will complete normally. The CE# signal must be driven high before issuing the WRDI command.

To execute a Write Disable operation, the host drives CE# low, issues the Write Disable command (04H) in SPI or QPI mode, and then drives CE# high. See Figure 5-45 and Figure 5-46 for the WRDI instruction sequence.

Figure 5-45. Write Disable Sequence (SPI)
Figure 5-46. Write Disable Sequence (QPI)
Note: C[1:0] = 04H