5.15 SPI Dual I/O Read (SDIOR)

The SPI Dual I/O Read operation is initiated in SPI mode by issuing the 8-bit command (BBH). After the command is received, the device switches to dual-I/O operation using SIO[1:0] and accepts three address bytes, followed by the Set Mode Configuration bits M[7:0]/dummy clocks, as defined in Table 5-8. The clock cycles used for mode configuration are included in the total dummy clock count. The number of dummy clock cycles depends on the operating frequency. The appropriate dummy clock setting must be programmed in Status Register 3, bits [1:0], prior to issuing this command. CE# must remain active-low for the duration of the SPI Dual Output Read. See Figure 5-11 for the SPI Dual Output Read sequence.

Following the dummy byte, the device outputs data on SIO[1:0], starting from the specified address. Data are continuously streamed through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments and wraps to the beginning of the address space after the highest memory address is reached.

The Set Mode Configuration bits M[7:0] determine whether the next instruction cycle is another SPI Dual I/O Read command. When M[5:4] = [1:0], the device expects the next continuous instruction to be another BBH Read command and does not require the opcode to be re-entered. In this mode, the host can initiate the next SDIOR cycle by driving CE# low, sending the three address bytes over the 2-bit bus, followed by the Set Mode Configuration bits M[7:0]/dummy clocks, as defined in Table 5-8. After the dummy clocks, the device outputs data starting from the specified address. There are no restrictions on address access in this mode. When M[5:4] is set to any value other than [1:0], the device expects the next instruction to be a new command. To exit or reset the Set Mode Configuration, the host drives CE# low, transmits FFFFH on SIO0 for sixteen clock cycles, and then drives CE# high. See Figure 5-12 for the SPI Dual I/O Mode Read sequence when M[5:4] = [1:0].