5.43 Read Security Register (RSR)

The Read Security Register (48H) instruction is supported in SPI mode and is used to read data from any of the three Security Registers. To perform a Read Security Register operation, the host drives CE# low, issues the RSR command (48H) in SPI mode, transmits three address bytes corresponding to the selected Security Register, and then provides eight dummy clock cycles. See Table 5-15 for the address mapping of the three Security Registers.

After the dummy cycles, the device outputs data on the falling edge of the SCK signal, starting from the specified address. The data stream is continuous across successive addresses, with the internal Address Pointer automatically incrementing until the highest address in the register is reached. At that point, the Address Pointer wraps back to 0x00 (the first byte of the register) and continues outputting data until the operation is terminated by a low-to-high transition on CE#.