5.16 SPI Quad Output Read (SQOR)

The SPI Quad Output Read instruction (6BH) requires the IOC bit in Status Register 2 to be set to 1 prior to command execution. The operation is initiated by issuing the 8-bit command (6BH), followed by three address bytes and eight dummy clock cycles. CE# must remain active-low for the duration of the SPI Quad Output Read operation. See Figure 5-13 for the SPI Quad Output Read sequence.

After the dummy clock cycles, the device outputs data on SIO[3:0], starting from the specified address. Data are continually streamed through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each data transfer. When the highest memory address is reached, the Address Pointer returns to the beginning of the address space.