5.4 Hold Operation

The HOLD# pin allows an active serial communication to be paused without resetting the clock sequence. When configured as a Hold pin, the RESET#/HOLD#/SIO3 pin provides this functionality. The HOLD# pin is always disabled in QPI mode and is supported only in SPI single-bit mode and SDI dual-bit mode.

To activate Hold mode, CE# must be in active-low state. Hold mode begins when the SCK active-low state coincides with the falling edge of the HOLD# signal. Hold mode ends when the rising edge of the HOLD# signal coincides with SCK being in active-low state.

If the falling edge of the HOLD# signal does not coincide with the SCK active-low state, the device enters Hold mode when SCK next reaches the active-low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active-low state, the device exits Hold mode when SCK next reaches the active-low state (see Figure 5-3).

While in Hold mode, the SO pin is placed in a high-impedance state, while the SI and SCK pins may be driven either low (V_IL) or high (V_IH). CE# must remain asserted low for the full duration of the Hold condition to preserve the internal logic state.

If CE# is driven active-high during a Hold condition, the device’s internal logic is reset. As long as HOLD# remains low, the device stays in Hold mode. To resume communication with the device, HOLD# must be driven active-high and CE# must be driven active-low.

Figure 5-3. Hold Operation