9.3.6.12 RX_CSRL_REG (in Host mode) Bit Definitions

Table 9-34. RX_CSRL_REG (Host)
Bit Number	Name	Function
7	ClrDataTog	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to reset the endpoint data toggle to 0.
6	RxStall	When a STALL handshake is received, this bit is set and an interrupt is generated. The Cortex-M3 processor (or fabric master) should clear this bit.
5	ReqPkt	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to request an IN transaction. It is cleared when RxPktRdy is set.
4	FlushFIFO	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to flush the latest packet from the endpoint receive FIFO. The FIFO pointer is reset and the RxPktRdy bit (bit 0 of this register) is cleared. FlushFIFO should only be used when RxPktRdy is set. At other times, it may cause data to be corrupted. If the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
3	DataError	While operating in ISO mode, this bit is set when RxPktRdy (bit 0 of this register) is set, if the data packet has a CRC or bit-stuff error, and cleared when RxPktRdy is cleared. In Bulk mode, this bit is set when the receive endpoint is halted, following the receipt of NAK responses for longer than the time set as the NAK limit by the RxInterval register. The Cortex-M3 processor (or fabric master) should clear this bit to allow the endpoint to continue. However, if double packet buffering is enabled, this alone will not allow the transfer to continue. In this case, the reqpkt bit should also be set in the same cycle this bit is cleared.
3	NAK Timeout
2	Error	The USB controller sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The Cortex-M3 processor (or fabric master) should clear this bit. This bit is only valid when the Rx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero.
1	FIFOFull	This bit is set when no more packets can be loaded into the receive FIFO.
0	RxPktRdy	This bit is set when a data packet has been received. The Cortex-M3 processor (or fabric master) should clear this bit when the packet has been unloaded from the receive FIFO. An interrupt is generated when the bit is set.