9.3.6.1 TX_MAX_P_REG Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| [15:11] | m-1 | N/A | If the core is configured with high-bandwidth
ISO/interrupt endpoints or packet splitting on bulk endpoints, the register
includes 2 or 5 further bits that define a multiplier m which is equal to one
more than the value recorded. For bulk endpoints with the packet splitting option enabled, the multiplier m can be up to 32 and defines the maximum number of USB packets (packets for transmission over the USB) of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. If the packet splitting option is not enabled, bits[15:13] are not implemented and bits[12:11] (if included) are ignored. The data packet must be an exact multiple of the payload specified by bits 10:0, which itself is required to be either 8, 16, 32, 64, or (in the case of high speed transfers) 512 bytes. For ISO/interrupts endpoints operating in High speed mode and with the high-bandwidth option enabled, m may only be 2 or 3 (corresponding to bit[11] set or bit[12] set) and it specifies the maximum number of such transactions that can take place in a single microframe. If either bit 11 or bit 12 is non-zero, the USB controller automatically splits any data packet written to the FIFO into 2 or 3 USB packets, each containing the specified payload (or less). The maximum payload for each transaction is 1,024 bytes, so this allows up to 3,072 bytes to be transmitted in each microframe. For ISO transfers in Full speed mode or if high-bandwidth is not enabled, bits[11] and [12] are ignored. The value written to bits[10:0] (multiplied by m in the case of high-bandwidth ISO transfers) must match the value given in the wMaxPacketSize field of the standard endpoint descriptor for the associated endpoint (see the USB specification v2.0). A mismatch could cause unexpected results. The total amount of data represented by the value written to this register (specified payload × m) must not exceed the FIFO size for the transmit endpoint, and should not exceed half the FIFO size if double-buffering is required. If this register is changed after packets have been sent from the endpoint, the transmit endpoint FIFO should be completely flushed (using the FlushFIFO bit, TX_CSRL_REG.bit[3]) after writing the new value to this register. |
| [10:0] | TxMaxP | m-1 | Maximum payload/transaction. Maximum payload in bytes transmitted in a single transaction. The value set can be up to 1,024 bytes but is subject to the constraints placed by the USB specification on packet sizes for bulk, interrupt, and ISO transfers in full speed and high speed operations. This must be set to an even number of bytes for proper interrupt generation DMA mode 1. |