9.3.6.15 RX_CSRH_REG (in Host mode) Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| 7 | AutoClear | 0 | If the Cortex-M3 processor (or fabric master) sets this bit, the RxPktRdy bit (bit 0 in RXCSRL_REG) will be automatically cleared when a packet of RxMaxP (RX_MAX_P_REG) bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RxPktRdy will have to be cleared manually. When using a DMA to unload the receive FIFO, data is read from the receive FIFO in 4-byte chunks regardless of the RxMaxP. Therefore, the RxPktRdy bit is cleared as shown in Table 9-36. Should not be set for high-bandwidth ISO endpoints. |
| 6 | AutoReq | 0 | If the Cortex-M3 processor (or fabric master) sets this bit, the ReqPkt bit (bit 5 in RX_CSRL_REG) will be set automatically when the RxPktRdy bit (bit 0 in RX_CSRL_REG) is cleared. This bit is automatically cleared when a short packet is received. |
| 5 | DMAReqEnab | 0 | The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA request for the receive endpoint. |
| 4 | PID Error | 0 | ISO transactions: The USB controller sets this bit to indicate a PID error in the received packet. Bulk/interrupt transactions: the setting of this bit is ignored. |
| 3 | DMAReqMode | 0 | The Cortex-M3 processor (or fabric master) sets this bit to select DMA Request mode 1 and clears it to select DMA Request mode 0. |
| 2 | Data Toggle Write Enable | 0 | The Cortex-M3 processor (or fabric master) writes a 1 to this bit to enable the current state of the endpoint0 data toggle to be written (refer to the Data Toggle bit, below). This bit is automatically cleared once the new value is written. |
| 1 | Data Toggle | 0 | When read, this bit indicates the current state of the endpoint0 data toggle. If Data Toggle Write Enable (bit[2] of this register) is high, this bit may be written with the required setting of the data toggle. If Data Toggle Write Enable is low, any value written to this bit is ignored. |
| 0 | IncompRx | 0 | This bit is set in a high-bandwidth ISO/interrupt transfer if the packet in the receive FIFO is incomplete because parts of the data were not received. It is cleared when RxPktRdy (bit 0 in RXCSRL_REG) is cleared. In anything other than ISO transfer, this bit always returns 0. |