9.3.6.8 TX_CSRH_REG (in Peripheral mode) Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| 7 | AutoSet | 0 | If the Arm®
Cortex®-M3 processor (or fabric master) sets this bit,
TxPktRdy (bit 0 of TXCSRL_REG) will be set automatically when data of the
maximum packet size (value in TxMaxP in TX_MAX_P_REG) is loaded into the
transmit FIFO. If a packet of less than the maximum packet size is loaded, then
TxPktRdy must be set manually. Should not be set for high-bandwidth ISO endpoints or high-bandwidth interrupt endpoints. |
| 6 | ISO | 0 | The Cortex-M3 processor (or fabric master) sets this bit to enable the transmit endpoint for ISO transfers, and clears it to enable the transmit endpoint for bulk or interrupt transfers. This bit only has effect in Peripheral mode. In Host mode, it always returns zero. |
| 5 | Mode | 0 | The Cortex-M3 processor (or fabric master)
sets this bit to enable the endpoint direction as transmit and clears the bit
to enable it as receive. This bit has effect only where the same endpoint FIFO is used for both transmit and receive transactions. |
| 4 | DMAReqEnab | 0 | The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA request for the transmit endpoint. |
| 3 | FrcDataTog | 0 | The Cortex-M3 processor (or fabric master) sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received or not. This can be used by interrupt transmit endpoints that are used to communicate rate feedback for ISO endpoints. |
| 2 | DMAReqMode | 0 | The Cortex-M3 processor (or fabric master)
sets this bit to select DMA request Mode 1 and clears it to select DMA request
Mode 0. This bit must not be cleared before or in the same cycle as the above DMAReqEnab bit (bit 4 of this register) is cleared. |
| [1:0] | Reserved | NA | NA |