9.3.6.13 RX_CSRH_REG (in Peripheral mode) Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| 7 | AutoClear | 0 | If the Cortex-M3 processor (or fabric master) sets this bit then the RxPktRdy bit (bit 0 in RXCSRL_REG) will be automatically cleared when a packet of RxMaxP (RX_MAX_P_REG) bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RxPktRdy will have to be cleared manually. When using a DMA to unload the receive FIFO, data is read from the receive FIFO in 4-byte chunks, regardless of the RxMaxP. Therefore, the RxPktRdy bit will be cleared, as shown in Table 9-36. Should not be set for high-bandwidth ISO endpoints. |
| 6 | ISO | 0 | The Cortex-M3 processor (or fabric master) sets this bit to enable the receive endpoint for ISO transfers, and clears it to enable the receive endpoint for bulk/interrupt transfers. |
| 5 | DMAReqEnab | 0 | The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA request for the receive endpoint. |
| 4 | DisNyet | 0 | Bulk/interrupt transactions: the Cortex-M3 processor (or fabric master) sets this bit to disable the sending of NYET handshakes. When set, all successfully received packets are ACKed, including the point at which the FIFO becomes full. This bit only has effect in High speed mode, and should be set for all interrupt endpoints. |
| PID Error | 0 | ISO transactions: the USB controller sets this bit to indicate a PID error in the received packet. | |
| 3 | DMAReqMode | 0 | The Cortex-M3 processor (or fabric master) sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. |
| [2:1] | Reserved | NA | — |
| 0 | IncompRx | 0 | This bit is set in a high-bandwidth ISO/interrupt transfer if the packet in the receive FIFO is incomplete because parts of the data were not received. It is cleared when RxPktRdy (bit0 in RXCSRL_REG) is cleared. In anything other than ISO transfer, this bit will always return 0. |