9.3.6.2 CSROL_REG (in Peripheral mode) Bit Definitions

Table 9-24. CSR0L_REG (Peripheral)
Bit Number	Name	Function
7	ServicedSetupEnd	The Arm® Cortex®-M3 processor (or fabric master) writes a 1 to this bit to clear the SetupEnd bit (bit[4] of this register). This bit is self clearing.
6	ServicedRxPktRdy	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to clear the RxPktRdy bit (bit[0] of this register). This bit is self clearing.
5	SendStall	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared automatically.
4	SetupEnd	This bit is set when a control transaction ends before the DataEnd bit (bit[3] of this register) has been set. An interrupt is generated and the FIFO is flushed at this time. The bit is cleared by the Cortex-M3 processor (or fabric master) writing a 1 to the ServicedSetupEnd bit (bit[7] of this register).
3	DataEnd	The Cortex-M3 processor (or fabric master) sets this bit: – When setting TxPktRdy (bit[1] of this register) for the last data packet. – When clearing RxPktRdy (bit[0] of this register) after unloading the last data packet. – When setting TxPktRdy (bit[1] of this register) for a zero length data packet. It is cleared automatically.
2	SentStall	This bit is set when a STALL handshake is transmitted. The Cortex-M3 processor (or fabric master) should clear this bit.
1	TxPktRdy	The Cortex-M3 processor (or fabric master) sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled).
0	RxPktRdy	This bit is set when a data packet has been received. An interrupt is generated when this bit is set. The Cortex-M3 processor (or fabric master) clears this bit by setting the ServicedRxPktRdy bit (bit[6]of this register).