9.3.6.5 CSROH_REG (in Host mode) Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| [7:4] | Reserved | N/A | — |
| 3 | Dis Ping | 0 | The Arm® Cortex®-M3 processor (or fabric master) writes a 1 to this bit to instruct the USB controller not to issue PING tokens in data and status phases of a high speed control transfer (for use with devices that do not respond to PING). |
| 2 | Data Toggle Write Enable | 0 | The Cortex-M3 processor (or fabric master) writes a 1 to this bit to enable the current state of the endpoint 0 data toggle to be written (refer to the Data Toggle bit). This bit is automatically cleared once the new value is written. |
| 1 | Data Toggle | 0 | When read, this bit indicates the current state of the endpoint 0 data toggle. If Data Toggle Write Enable (bit 2 of this register) is High, this bit may be written with the required setting of the data toggle. If Data Toggle Write Enable is Low, any value written to this bit is ignored. |
| 0 | FlushFIFO | 0 | The Cortex-M3 processor (fabric master) writes a 1 to this bit to flush the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and the TxPktRdy/RxPktRdy bit (bit 1 and bit 0 of CSR0L_REG) is cleared. FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other times, it may cause data to be corrupted. |