9.3.6.4 CSROH_REG (in Peripheral mode) Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| [7:1] | Reserved | N/A | — |
| 0 | FlushFIFO | 0 | The Arm®
Cortex®-M3 processor (fabric master) writes a 1 to this
bit to flush the next packet to be transmitted/read from the endpoint 0 FIFO.
The FIFO pointer is reset and the TxPktRdy/RxPktRdy bit (bit[1] and bit[0] of
CSR0L_REG) is cleared. FlushFIFO should only be used when TxPktRdy/RxPktRdy is set. At other times, it may cause data to be corrupted. |