9.3.6.9 TX_CSRH_REG (in Host mode) Bit Definitions

Table 9-31. TX_CSRH_REG (Host)
Bit Number	Name	Reset Value	Function
7	AutoSet	0	If the Arm® Cortex®-M3 processor (or fabric master) sets this bit, TxPktRdy (bit0 of TXCSRL_REG) will be set automatically when data of the maximum packet size (value in TxMaxP of TX_MAX_P_REG) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then TxPktRdy must be set manually. Note: Should not be set for high-bandwidth ISO endpoints or high-bandwidth interrupt endpoints.
6	Reserved	NA	—
5	Mode	0	The Cortex-M3 processor (or fabric master) sets this bit to enable the endpoint direction as transmit and clears the bit to enable it as receive. This bit has effect only where the same endpoint FIFO is used for both transmit and receive transactions.
4	DMAReqEnab	0	The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA request for the transmit endpoint.
3	FrcDataTog	0	The Cortex-M3 processor (or fabric master) sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received or not. This can be used by Interrupt transmit endpoints that are used to communicate rate feedback for ISO endpoints.
2	DMAReqMode	0	The Cortex-M3 processor (or fabric master) sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. This bit must not be cleared either before or in the same cycle as the above DMAReqEnab bit (bit4 of this register) is cleared.
1	Data Toggle Write Enable	0	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to enable the current state of the endpoint 0 data toggle to be written (see Data Toggle bit). This bit is automatically cleared once the new value is written.
0	Data Toggle	0	When read, this bit indicates the current state of the endpoint 0 data toggle. If Data Toggle Write Enable (bit 1 of this register) is High, this bit may be written with the required setting of the data toggle. If Data Toggle Write Enable is Low, any value written to this bit is ignored.

7

AutoSet

0

If the Arm® Cortex®-M3 processor (or fabric master) sets this bit, TxPktRdy (bit0 of TXCSRL_REG) will be set automatically when data of the maximum packet size (value in TxMaxP of TX_MAX_P_REG) is loaded into the transmit FIFO. If a packet of less than the maximum packet size is loaded, then TxPktRdy must be set manually.

Note: Should not be set for high-bandwidth ISO endpoints or high-bandwidth interrupt endpoints.

6

Reserved

NA

—

5

Mode

0

The Cortex-M3 processor (or fabric master) sets this bit to enable the endpoint direction as transmit and clears the bit to enable it as receive.

This bit has effect only where the same endpoint FIFO is used for both transmit and receive transactions.

4

DMAReqEnab

0

The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA request for the transmit endpoint.

3

FrcDataTog

0

The Cortex-M3 processor (or fabric master) sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received or not. This can be used by Interrupt transmit endpoints that are used to communicate rate feedback for ISO endpoints.

2

DMAReqMode

0

The Cortex-M3 processor (or fabric master) sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0.

This bit must not be cleared either before or in the same cycle as the above DMAReqEnab bit (bit4 of this register) is cleared.

1

Data Toggle Write Enable

0

The Cortex-M3 processor (or fabric master) writes a 1 to this bit to enable the current state of the endpoint 0 data toggle to be written (see Data Toggle bit). This bit is automatically cleared once the new value is written.

0

Data Toggle

0

When read, this bit indicates the current state of the endpoint 0 data toggle. If Data Toggle Write Enable (bit 1 of this register) is High, this bit may be written with the required setting of the data toggle. If Data Toggle Write Enable is Low, any value written to this bit is ignored.