9.3.6.6 TX_CSRL_REG (in Peripheral mode) Bit Definitions

Table 9-28. TX_CSRL_REG (Peripheral)
Bit NumberNameReset ValueFunction
7IncompTx0When the endpoint is being used for high-bandwidth ISO transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts.

In anything other than ISO transfers, this bit will always return 0.

6ClrDataTog0The Arm® Cortex®-M3 processor (or fabric master) writes a 1 to this bit to reset the endpoint data toggle to 0.
5SentStall0This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit (bit 0 of this register) is cleared. The Cortex-M3 processor (or fabric master) should clear this bit.
4SendStall0The Cortex-M3 processor (or fabric master) writes a 1 to this bit to issue a STALL handshake to an IN token. The Cortex-M3 processor (or fabric master) clears this bit to terminate the stall condition.

This bit has no effect where the endpoint is being used for ISO transfers.

3FlushFIFO0The Cortex-M3 processor (or fabric master) writes a 1 to this bit to flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, the TxPktRdy bit (bit0 of this register) is cleared and an interrupt is generated. It may be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO.

FlushFIFO should only be used when TxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.

2UnderRun0The controller sets this bit if an IN token is received when TxPktRdy (bit0 of this register) is not set. The Cortex-M3 processor (or fabric master) should clear this bit.
1FIFONotEmpty0The controller sets this bit when there is at least 1 packet in the transmit FIFO.
0TxPktRdy0The Cortex-M3 processor (or fabric master) sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated at this point (if enabled). TxPktRdy is automatically cleared prior to loading a second packet into a double-buffered FIFO.