9.3.6.7 TX_CSRL_REG (in Host mode) Bit Definitions

Table 9-29. TX_CSRL_REG (Host)
Bit Number	Name	Function
7	NAK Timeout	(Bulk endpoints only) This bit will be set when the transmit endpoint is halted, following the receipt of responses for longer than the time set as the NAK Limit by the TxInterval register. The Arm® Cortex®-M3 processor (or fabric master) should clear this bit to allow the endpoint to continue.
7	IncompTx	(High-bandwidth interrupt endpoints only) This bit will be set if no response is received from the device to which the packet is being sent.
6	ClrDataTog	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to reset the endpoint data toggle to 0.
5	RxStall	This bit is set when a STALL handshake is received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed and the TxPktRdy bit (bit 0 of this register) is cleared. The Cortex-M3 processor (or fabric master) should clear this bit.
4	SetupPkt	The Cortex-M3 processor (or fabric master) sets this bit at the same time the TxPktRdy bit (bit 0 of the register) is set, to send a SETUP token instead of an OUT token for the transaction. Setting this bit also clears the Data Toggle.
3	FlushFIFO	The Cortex-M3 processor (or fabric master) writes a 1 to this bit to flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, the TxPktRdy bit (bit0 of this register) is cleared and an interrupt is generated. May be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO. FlushFIFO should only be used when TxPktRdy is set. At other times, it may cause data to be corrupted. Also note that, if the FIFO is double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
2	Error	The controller sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. When the bit is set, an interrupt is generated, TxPktRdy (bit 0 of this register) is cleared and the FIFO is completely flushed. The Cortex-M3 processor (or fabric master) should clear this bit. Valid only when the endpoint is operating in Bulk or Interrupt mode.
1	FIFONotEmpty	The controller sets this bit when there is at least 1 packet in the transmit FIFO.
0	TxPktRdy	The Cortex-M3 processor (or fabric master) sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). TxPktRdy is also automatically cleared prior to loading a second packet into a double-buffered FIFO.