9.3.6.3 CSROL_REG (Host mode) Bit Definitions

Table 9-25. CSR0L_REG (Host)
Bit Number	Name	Function
7	NAK Timeout	This bit is set when endpoint 0 is halted, following the receipt of NAK responses for longer than the time set by the NAKLimit0 register. The Arm® Cortex®-M3 processor (or fabric master) should clear this bit to allow the endpoint to continue.
6	StatusPkt	The Cortex-M3 processor (or fabric master) sets this bit at the same time as the TxPktRdy (bit[1] of this register) or ReqPkt bit (bit 0 of this register) is set, to perform a status stage transaction. Setting this bit ensures that the data toggle is set to 1 so that a DATA1 packet is used for the status stage transaction.
5	ReqPkt	The Cortex-M3 processor (or fabric master) sets this bit to request an IN transaction. It is cleared when RxPktRdy (bit [0] of this register) is set.
4	Error	This bit will be set when three attempts have been made to perform a transaction with no response from the peripheral. The Cortex-M3 processor (or fabric master) should clear this bit. An interrupt is generated when this bit is set.
3	SetupPkt	The Cortex-M3 processor (or fabric master) sets this bit, at the same time as the TxPktRdy bit (bit[1] of this register) is set, to send a SETUP token instead of an OUT token for the transaction. Setting this bit also clears the Data Toggle.
2	RxStall	This bit is set when a STALL handshake is received. The Cortex-M3 processor (or fabric master) should clear this bit.
1	TxPktRdy	The Cortex-M3 processor (or fabric master) sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled).
0	RxPktRdy	This bit is set when a data packet has been received. An interrupt is generated (if enabled) when this bit is set. The Cortex-M3 processor (or fabric master) should clear this bit when the packet has been read from the FIFO.