5.6.11 Dummy Control (DC0, DC1)
The Dummy Cycle control bits (DC1 and DC0) define the number of dummy clock cycles required for read operations and are selected based on the maximum operating frequency of the Read command (see Table 5-8).
| Dummy Clocks - DC[1:0] | High Speed Read, SPI Dual Output Read, SPI Quad Output Read (Number of Dummy Clocks/Max. Clock Frequency) | SPI Dual I/O Read, Word Quad I/O Read, (Number of Dummy Clocks/Max. Clock Frequency) | Fast Quad I/O Read, (Number of Dummy Clocks/Max. Clock Frequency) | DTR Fast Read, DTR Fast Dual I/O Read (Number of Dummy Clocks/Max. Clock Frequency) | DTR Fast Quad I/O Read (Number of Dummy Clocks/Max. Clock Frequency) |
|---|---|---|---|---|---|
| 00 (Default) | 8,166 MHz | 4,108 MHz | 6,166 MHz | 6,90 MHz | 8,90 MHz |
| 01 | 8,166 MHz | 8,166 MHz | 4,108 MHz | 4,66 MHz | 4, 66 MHz |
| 10 | 8,166 MHz | 4,108 MHz | 8,166 MHz | 8,90 MHz | 6, 66 MHz |
| 11 | 8, 166 MHz | 8,166 MHz | 10,166 MHz | 10,108 MHz | 10, 108 MHz |