LAN8670/1

Description
Conformity
1 Preface
2 Introduction
3 Pin Description and Configuration
4 Functional Descriptions
5 Register Descriptions
- 5.1 SMI Basic Control and Status Registers
- 5.2 PMA/PMD Registers
- 5.3 PCS Registers
- 5.4 Miscellaneous Registers
  - 5.4.1 Configuration Protection Control
    Configuration Protection Control
  - 5.4.2 Control 1 Register
    Control 1 Register
  - 5.4.3 Control 1 Register - Rev D
    Control 1 Register - Rev D
  - 5.4.4 Pin Control Register
    Pin Control Register
  - 5.4.5 Link Status Control - Rev D
    Link Status Control - Rev D
  - 5.4.6 Status 1 Register
    Status 1 Register
  - 5.4.7 Status 1 Register - Rev D
    Status 1 Register - Rev D
  - 5.4.8 Status 2 Register
    Status 2 Register
  - 5.4.9 Status 2 Register - Rev D
    Status 2 Register - Rev D
  - 5.4.10 Status 3 Register
    Status 3 Register
  - 5.4.11 Interrupt Mask 1 Register
    Interrupt Mask 1 Register
  - 5.4.12 Interrupt Mask 1 Register - Rev D
    Interrupt Mask 1 Register - Rev D
  - 5.4.13 Interrupt Mask 2 Register
    Interrupt Mask 2 Register
  - 5.4.14 Interrupt Mask 2 Register - Rev D
    Interrupt Mask 2 Register - Rev D
  - 5.4.15 Counter Control Register
    Counter Control Register
  - 5.4.16 Transmit Opportunity Count (High)
    Transmit Opportunity Count (High)
  - 5.4.17 Transmit Opportunity Count (Low)
    Transmit Opportunity Count (Low)
  - 5.4.18 BEACON Count (High)
    BEACON Count (High)
  - 5.4.19 BEACON Count (Low)
    BEACON Count (Low)
  - 5.4.20 PLCA Multiple ID 0 Register
    PLCA Multiple ID 0 Register
  - 5.4.21 PLCA Multiple ID 1 Register
    PLCA Multiple ID 1 Register
  - 5.4.22 PLCA Multiple ID 2 Register
    PLCA Multiple ID 2 Register
  - 5.4.23 PLCA Multiple ID 3 Register
    PLCA Multiple ID 3 Register
  - 5.4.24 PLCA Reconciliation Sublayer Control 1
    PLCA Reconciliation Sublayer Control 1
  - 5.4.25 PLCA Reconciliation Sublayer Control 1 - Rev D
    PLCA Reconciliation Sublayer Control 1 - Rev D
  - 5.4.26 PLCA Reconciliation Sublayer Status
    PLCA Reconciliation Sublayer Status
  - 5.4.27 Port Management 2
    Port Management 2
  - 5.4.28 Port Management 2 - Rev D
    Port Management 2 - Rev D
  - 5.4.29 Inactivity Watchdog Timeout (High)
    Inactivity Watchdog Timeout (High)
  - 5.4.30 Inactivity Watchdog Timeout (High) - Rev D
    Inactivity Watchdog Timeout (High) - Rev D
  - 5.4.31 Inactivity Watchdog Timeout (Low)
    Inactivity Watchdog Timeout (Low)
  - 5.4.32 Inactivity Watchdog Timeout (Low) - Rev D
    Inactivity Watchdog Timeout (Low) - Rev D
  - 5.4.33 Transmit Match Control Register
    Transmit Match Control Register
  - 5.4.34 Transmit Match Pattern (High) Register
    Transmit Match Pattern (High) Register
  - 5.4.35 Transmit Match Pattern (Low) Register
    Transmit Match Pattern (Low) Register
  - 5.4.36 Transmit Matched Packet Delay Register
    Transmit Matched Packet Delay Register
  - 5.4.37 Receive Match Control Register
    Receive Match Control Register
  - 5.4.38 Receive Match Pattern (High) Register
    Receive Match Pattern (High) Register
  - 5.4.39 Receive Match Pattern (Low) Register
    Receive Match Pattern (Low) Register
  - 5.4.40 Receive Matched Packet Delay Register
    Receive Matched Packet Delay Register
  - 5.4.41 Credit Based Shaper Stop Threshold (High) Register
    Credit Based Shaper Stop Threshold (High) Register
  - 5.4.42 Credit Based Shaper Stop Threshold (Low) Register
    Credit Based Shaper Stop Threshold (Low) Register
  - 5.4.43 Credit Based Shaper Start Threshold (High) Register
    Credit Based Shaper Start Threshold (High) Register
  - 5.4.44 Credit Based Shaper Start Threshold (Low) Register
    Credit Based Shaper Start Threshold (Low) Register
  - 5.4.45 Credit Based Shaper Slope Control Register
    Credit Based Shaper Slope Control Register
  - 5.4.46 Credit Based Shaper Top Limit (High) Register
    Credit Based Shaper Top Limit (High) Register
  - 5.4.47 Credit Based Shaper Top Limit (Low) Register
    Credit Based Shaper Top Limit (Low) Register
  - 5.4.48 Credit Based Shaper Bottom Limit (High) Register
    Credit Based Shaper Bottom Limit (High) Register
  - 5.4.49 Credit Based Shaper Bottom Limit (Low) Register
    Credit Based Shaper Bottom Limit (Low) Register
  - 5.4.50 Credit Based Shaper Credit Counter (High) Register
    Credit Based Shaper Credit Counter (High) Register
  - 5.4.51 Credit Based Shaper Credit Counter (Low) Register
    Credit Based Shaper Credit Counter (Low) Register
  - 5.4.52 Credit Based Shaper Control Register
    Credit Based Shaper Control Register
  - 5.4.53 PLCA Skip Control Register
    PLCA Skip Control Register
  - 5.4.54 PLCA Transmit Opportunity Skip Register
    PLCA Transmit Opportunity Skip Register
  - 5.4.55 Application Controlled Media Access Control Register
    Application Controlled Media Access Control Register
  - 5.4.56 Sleep Control 0 Register
    Sleep Control 0 Register
  - 5.4.57 Sleep Control 0 Register - Rev D
    Sleep Control 0 Register - Rev D
  - 5.4.58 Sleep Control 1 Register
    Sleep Control 1 Register
  - 5.4.59 Sleep Control 1 Register - Rev D
    Sleep Control 1 Register - Rev D
  - 5.4.60 Collision Detector Control 0 Register
    Collision Detector Control 0 Register
  - 5.4.61 Collision Detector Control 0 Register - Rev D
    Collision Detector Control 0 Register - Rev D
  - 5.4.62 SQI Control Register
    SQI Control Register
  - 5.4.63 SQI Control Register - Rev D
    SQI Control Register - Rev D
  - 5.4.64 SQI Status 0 Register
    SQI Status 0 Register
  - 5.4.65 SQI Status 0 Register - Rev D
    SQI Status 0 Register - Rev D
  - 5.4.66 SQI Configuration 0 Register
    SQI Configuration 0 Register
  - 5.4.67 SQI Configuration 0 Register - Rev D
    SQI Configuration 0 Register - Rev D
  - 5.4.68 SQI Configuration 2 Register
    SQI Configuration 2 Register
  - 5.4.69 SQI Configuration 2 Register - Rev D
    SQI Configuration 2 Register - Rev D
  - 5.4.70 Pad Control 3 Register
    Pad Control 3 Register
  - 5.4.71 Analog Control 5
    Analog Control 5
  - 5.4.72 OPEN Alliance Map ID and Version Register
    OPEN Alliance Map ID and Version Register
  - 5.4.73 OPEN Alliance Map ID and Version Register - Rev D
    OPEN Alliance Map ID and Version Register - Rev D
  - 5.4.74 PLCA Control 0 Register
    PLCA Control 0 Register
  - 5.4.75 PLCA Control 1 Register
    PLCA Control 1 Register
  - 5.4.76 PLCA Status Register
    PLCA Status Register
  - 5.4.77 PLCA Transmit Opportunity Timer Register
    PLCA Transmit Opportunity Timer Register
  - 5.4.78 PLCA Burst Mode Register
    PLCA Burst Mode Register
  - 5.4.79 PLCA Diagnostics Register - Rev D
    PLCA Diagnostics Register - Rev D
  - 5.4.80 Advanced Diagnostic Features Capability - Rev D
    Advanced Diagnostic Features Capability - Rev D
  - 5.4.81 Harness Defect Detection - Rev D
    Harness Defect Detection - Rev D
  - 5.4.82 Dynamic Channel Quality Transmit Opportunity ID Register - Rev D
    Dynamic Channel Quality Transmit Opportunity ID Register - Rev D
  - 5.4.83 Signal Quality Index Register - Rev D
    Signal Quality Index Register - Rev D
  - 5.4.84 Signal Quality Index Plus Register - Rev D
    Signal Quality Index Plus Register - Rev D
  - 5.4.85 Topology Discovery Control Register - Rev D
    Topology Discovery Control Register - Rev D
  - 5.4.86 Topology Discovery Status Register - Rev D
    Topology Discovery Status Register - Rev D
  - 5.4.87 Topology Discovery Distance measurement Result Register (Low) - Rev D
    Topology Discovery Distance measurement Result Register (Low) - Rev D
  - 5.4.88 Topology Discovery Distance measurement Result Register (High) - Rev D
    Topology Discovery Distance measurement Result Register (High) - Rev D
  - 5.4.89 Topology Discovery Internal Delay Result Register (Low) - Rev D
    Topology Discovery Internal Delay Result Register (Low) - Rev D
  - 5.4.90 Topology Discovery Internal Delay Result Register (High) - Rev D
    Topology Discovery Internal Delay Result Register (High) - Rev D
  - 5.4.91 Topology Discovery Measured Node Delay measurement Result Register (Low) - Rev D
    Topology Discovery Measured Node Delay measurement Result Register (Low) - Rev D
  - 5.4.92 Topology Discovery Measured Node Delay measurement Result Register (High) - Rev D
    Topology Discovery Measured Node Delay measurement Result Register (High) - Rev D
  - 5.4.93 Topology Discovery Measured Node Measurement Duration Register - Rev D
    Topology Discovery Measured Node Measurement Duration Register - Rev D
  - 5.4.94 Topology Discovery Advanced Control Register - Rev D
    Topology Discovery Advanced Control Register - Rev D
  - 5.4.95 Wake Sleep Status Register - Rev D
    Wake Sleep Status Register - Rev D
  - 5.4.96 Wake Sleep Control Register
    Wake Sleep Control Register
6 Application Information
7 Operational Characteristics
8 Packaging Information
9 Package Marking Information
Product Identification System
Data Sheet Revision History
Microchip Information

5.4.81 Harness Defect Detection - Rev D

This register is only valid for devices of Revision D0 and later.

Name:	HDD - Rev D
Address:	0xCC01


Bit	15	14	13	12	11	10	9	8
	HDDREQ	HDDRDY	START
Access	R/W	RO	R/W SC	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
						VALID	SHTOPNSTS[1:0]
Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bit 15 – HDDREQ HDD Request

Setting this bit requests the PMA to enter the HDD diagnostic mode. When the PMA has successfully entered the HDD diagnostic mode, the HDDRDY bit will be set. Similarly, writing a ‘0’ to this bit will return the PMA to normal operation and will be verified by the HDDRDY returning ‘0’.

Value	Description
`0`	PMA in normal mode - HDD not requested
`1`	Request PMA to enter the HDD diagnostic mode

Bit 14 – HDDRDY HDD Ready

When this bit is set it indicates that the PMA is in the HDD diagnostic mode. When clear, the PMA is in normal mode. This bit is used to feed back the current state of the PMA as controlled by the HDDREQ bit.

Value	Description
`0`	PMA in normal mode - HDD is not ready
`1`	PMA is in HDD diagnostic mode - HDD is ready

Bit 13 – START Start HDD measurement

Writing a ‘1’ to this bit will start the HDD measurement process. Once set, it will automatically be cleared to ‘0’ once the process has completed. Upon completion, if there is no error, the VALID bit will be set.

Value	Description
`0`	HDD measurement not in progress
`1`	HDD measurement in progress

Bit 2 – VALID Valid HDD Measurement Results

When this bit is set, the value in the SHTOPNSTS field is valid and may be read. This bit is cleared when the measurement process is started by setting the START bit.

Value	Description
`0`	Measurement not valid
`1`	Measurement results are valid

Bits 1:0 – SHTOPNSTS[1:0] Short Open State

This field returns the open/short state of the cable harness.

Value	Description
`00`	No fault detected
`01`	Fault detected - Open or missing termination(s)
`10`	Fault detected - Short or extra termination(s)
`11`	Fault detected - type undetermined

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.