5.19 High-Speed Read with 4-Byte Address
The High-Speed Read instruction (0CH) is supported in SPI mode.
To initiate a High-Speed Read operation, the host transmits the 8-bit command (0CH), followed by a 4-byte address and eight dummy clocks. Refer to Figure 5-12 for the SPI High-Speed Read sequence. After the dummy cycles, the device outputs data on SIO[1] on the falling edge of the SCK signal, beginning at the specified address location. Data continues streaming through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each byte read. When the highest memory address is reached, the Address Pointer wraps around to address location 00000000H.