5.1 Device Operation

The MC25VF256 supports both Serial Peripheral Interface (SPI) mode and a 4-bit multiplexed QPI mode. To maintain backward compatibility with traditional SPI Serial Flash devices, the device defaults to SPI mode after a Power-On Reset (POR). In SPI mode, the device supports multi-I/O (x1/x2/x4) read and write commands. A dedicated command instruction is used to configure the device for QPI mode. Data flow in QPI mode is similar to SPI mode; however, QPI mode uses four multiplexed I/O signals for command, address and data transfer operations.

The MC25VF256 supports both Mode 0 (0,0) and Mode 3 (1,1) bus operations in SPI and QPI modes. The difference between the two modes is the state of the SCK signal when the bus host is in standby mode and no data transfer is occurring. In Mode 0, the SCK signal remains low during standby, while in Mode 3, the SCK signal remains high. In both modes, the Serial Data I/O signals (SIO[3:0]) are sampled on the rising edge of the SCK clock signal for input operations and driven after the falling edge of the SCK clock signal for output operations. Traditional SPI mode uses separate input (SI) and output (SO) data signals, as shown in Figure 5-1. QPI mode uses four multiplexed signals, SIO[3:0], for both input and output data transfers, as shown in Figure 5-2. As a result, QPI mode provides four times the data transfer throughput of traditional SPI mode at the same clock frequency, without requiring additional package pins.