5.11 Reset Enable (RSTEN) and Reset (RST)

The Reset operation provides a software-based system reset that returns the device to normal Ready mode. This functionality is supported in both SPI and QPI modes and requires two commands issued sequentially: Reset Enable (RSTEN) followed by Reset (RST).

To initiate a reset, the host drives CE# low and transmits the Reset Enable command (66H) in either SPI or QPI mode, then drives CE# high. The host then drives CE# low again, transmits the Reset command (99H), and finally drives CE# high. Figure 5-5 illustrates the sequence in QPI mode, while Table 5-3 summarizes the device status after a software reset.

Executing a device reset restores the device to its default power-on state and clears all volatile settings, including Volatile Status Register bits, Write Enable Latch (WEL), Program/Erase Suspend status, Read Parameter settings (P7–P0) and Wrap Bit settings (W6–W4). If a reset is issued during an active Program or Erase operation, the operation is terminated. This may cause data corruption or data loss within the affected memory region.

Reset recovery time depends on the operation that was active before the reset. Recovery from a Write operation requires more time than recovery from other operations. Refer to Table 6-9 for detailed reset timing parameters.

Figure 5-5. Reset Sequence

Note: C[1:0] = 66H; C[3:2] = 99H