5.20 SPI Dual Output Read (SDOR)

The SPI Dual Output Read operation is initiated by issuing the 8-bit command (3BH), followed by three or four address bytes and eight dummy clock cycles. CE# must remain active-low throughout the entire SPI Dual Output Read operation. Refer to Figure 5-13 for the command sequence.

Following the dummy clock cycles, the device outputs data on SIO[1:0], beginning at the specified address. Data continues streaming through successive addresses until the operation is terminated by a low‑to‑high transition on CE#. The internal Address Pointer automatically increments after each data transfer. When the highest memory address is reached, the Address Pointer returns to the beginning of the address space.