The Block Erase_32KB instruction clears all bits within the selected 32-KB block to 1. If the selected memory region is protected, the Block Erase_32KB instruction is ignored. Before initiating any erase or write operation, the Write Enable (WREN) instruction must be executed. The CE# signal must remain asserted low throughout the entire command sequence.
To perform a Block Erase_32KB operation, the host asserts CE# low and transmits the Block Erase command (52H), followed by either three or four address bytes, and then drives CE# high to begin the internal erase operation. Address bits [AMS-A15], where AMS represents the Most Significant Address bit, define the block address. The remaining lower address bits can be VIL or VIH. Completion of the internally timed Block Erase_32KB operation can be determined by polling the Busy bit in the status register or by waiting for the specified block erase time TBE32KB. Refer to Figure 5-40 and Figure 5-41 for the Block Erase timing sequences.Figure 5-40. Block Erase Sequence (SPI)
Note: MSb = Most Significant bit
Figure 5-41. Block Erase Sequence (QPI)
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 52H
DS20007183A
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