5.30 DTR Fast Dual I/O Read (DTR_FDIOR)

The DTR Fast Dual I/O Read (DTR_FDIOR) instruction is initiated by issuing the 8-bit command BDH in SPI mode. Once the command is accepted, the device switches to 2-bit I/O operation with Dual Transfer Rate (DTR) mode to receive a 3-byte address, followed by the Set Mode Configuration bits M[7:0] and the required dummy clock cycles. The clock cycles used to transmit the Set Mode Configuration bits are included in the total dummy clock count. The number of dummy clock cycles depends on the operating frequency, as specified in Table 5-7. Prior to issuing this command, the appropriate dummy clock configuration must be programmed into Status Register 3 bits [1:0]. The CE# signal must remain asserted low throughout the entire DTR Fast Dual I/O Read operation. Refer to Figure 5-30 for the detailed timing sequence.

After the dummy cycles, the device outputs data on SIO[1:0] using dual data rate transfer, beginning at the specified address location. Data is streamed continuously across sequential memory addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments and wraps to the beginning of the address space after reaching the highest memory address.

The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle continues as another DTR Fast Dual I/O Read operation. When M[5:4] = [1:0], the device interprets the next continuous instruction as another BDH read command, and the opcode does not need to be retransmitted. In this mode, the host initiates the next DTR_FDIOR cycle by asserting CE# low and transmitting the 2-bit-wide input for the 3-byte address, followed by the Set Mode Configuration bits M[7:0] and the required dummy clock cycles. After the dummy cycles, the device begins outputting data from the specified address location. Address access is unrestricted.

If M[5:4] is set to any value other than [1:0], the device expects the next operation to begin with a new command instruction. To exit or reset the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for twenty clock cycles, and then deassert CE# high.