5.18 High-Speed Read

The High-Speed Read instruction (0BH) is supported in both SPI and QPI modes. In SPI mode, the operation begins when the host transmits the 8-bit command (0BH), followed by three address bytes and eight dummy clock cycles. After the dummy clock cycles, the device outputs data on SIO[1] on the falling edge of the SCK, starting from the specified address. Data continues streaming through sequential addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each byte read. When the highest memory address is reached, the Address Pointer wraps around to address location 000000H. Refer to Figure 5-10 for the SPI High-Speed Read sequence.

In QPI mode, the host initiates the operation by driving CE# low and sending the Read command (0BH), followed by three or four address bytes and a programmable number of dummy clock cycles. The number of dummy cycles (4, 6, 8 or 10) is configured using the Set Read Parameters instruction (C0H) and depends on the operating frequency. Refer to Figure 5-11 for the QPI High-Speed Read sequence. After the dummy clock cycles in QPI mode, the device outputs data on SIO[3:0] on the falling edge of SCK, beginning at the specified address. Data continues streaming through successive addresses until terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each data unit. Once the highest memory address is reached, the Address Pointer returns to address location 000000H.