5.31 DTR Fast Quad I/O Read (DTR_FQIOR)
The DTR Fast Quad I/O Read (DTR_FQIOR) instruction requires the IOC bit in
Status Register 2 to be set to 1 before the command is executed. The
operation is initiated by issuing the 8-bit command EDH in SPI mode. After the command
is accepted, the device switches to 4-bit I/O mode with Dual Transfer Rate (DTR)
operation to receive either a three-byte or four-byte address, followed by the Set Mode
Configuration bits M[7:0] and the required dummy clock cycles. The clock cycles used for
transmitting the Set Mode Configuration bits are included in the total dummy clock
count. The number of dummy clock cycles depends on the operating frequency, as specified
in Table 5-7. Before issuing this command, the appropriate dummy clock
configuration must be programmed into Status Register 3 bits [1:0]. The CE# signal must
remain asserted low throughout the entire DTR Fast Quad I/O Read operation. Refer to
Figure 5-31 for the detailed timing sequence.
After the dummy cycles, the device outputs data on SIO[3:0] using dual data rate transfer, beginning at the specified address location. Data is continuously streamed across sequential memory addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments and wraps to the beginning of the address space after reaching the highest memory address.
The Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle continues as another DTR Fast Quad I/O Read operation. When M[5:4] = [1:0], the device interprets the next continuous instruction as another EDH read command, and the opcode does not need to be retransmitted. In this mode, the host initiates the next DTR_FQIOR cycle by asserting CE# low and transmitting the 4-bit-wide address input for either three or four address bytes, followed by the Set Mode Configuration bits M[7:0] and the required dummy clock cycles. After the dummy cycles, the device outputs data beginning at the specified address location. Address access is unrestricted.
If M[5:4] is set to any value other than [1:0], the device expects the next instruction cycle to begin with a new command opcode. To exit or reset the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for ten clock cycles, and then deassert CE# high. Refer to Figure 5-32 for the DTR Fast Quad I/O Mode Read sequence when M[5:4] = [1:0].
In QPI mode, the host initiates the operation by asserting CE# low and transmitting the Read command EDH. The device then switches to 4-bit I/O mode with dual data rate operation to receive either a three-byte or four-byte address, followed by the Set Mode Configuration bits M[7:0] and dummy clock cycles configured through the Set Read Parameters instruction (C0H), as defined in Table 5-12. The number of required dummy cycles varies according to the operating frequency. Refer to Figure 5-32 for the QPI mode timing sequence. After the dummy cycles in QPI mode, the device outputs data on SIO[3:0] on the falling edge of the SCK signal, beginning at the specified address location.
As in SPI mode, the Set Mode Configuration bits M[7:0] determine whether the subsequent instruction cycle continues as another DTR Fast Quad I/O Read operation. When M[5:4] = [1:0], the device expects the next continuous instruction to be another EDH read command without requiring the opcode to be retransmitted. The host may initiate the next DTR_FQIOR cycle by asserting CE# low and transmitting the 4-bit-wide address input, followed by the Set Mode Configuration bits M[7:0] and dummy clock cycles. After the dummy cycles, the device outputs data from the specified address location without address access restrictions.
If M[5:4] contains any value other than [1:0], the device expects the next instruction cycle to begin with a new command instruction. To reset or exit the Set Mode Configuration, assert CE# low, transmit FFH on SIO0 for ten clock cycles, and then deassert CE# high.