5.44 Serial Flash Discoverable Parameters (SFDP)

The Serial Flash Discoverable Parameters (SFDP) instruction provides information describing the characteristics and capabilities of the device. SFDP enables device-independent, JEDEC ID-independent, and forward/backward-compatible software support for current and future Serial Flash device families.

In SPI mode, the SFDP operation is initiated by issuing the 8-bit command 5AH, followed by a 24-bit address A[23:0] transmitted over 24 clock cycles, and then eight dummy clock cycles. After the dummy cycles, the device immediately outputs SFDP data on the falling edge of the SCK signal. The CE# signal must remain active-low throughout the entire SFDP operation. Refer to Figure 5-38 for the SFDP timing sequence.

In QPI mode, the SFDP read operation is initiated by issuing the 8-bit command 5AH, followed by a three-byte address with a value of 000000H. This is followed by dummy clock cycles configured through the Set Read Parameters (C0H) instruction, as defined in Table 5-12. The required number of dummy clock cycles varies according to the operating frequency. After the dummy cycles in QPI mode, the device outputs the SFDP data.