5.64 Erase Security Register (ESR)

The Erase Security Register instruction is supported in both SPI and QPI modes and is used to erase Security Register 1, Security Register 2 or Security Register 3. The device ignores any Erase Security Register instruction that targets an invalid or protected address. Refer to Table 5-16 for valid Security Register address ranges. Address bits A10 through A0 are treated as “don’t care” during the Erase Security Register operation. Before initiating the operation, the WREN instruction must be executed.

To execute an Erase Security Register operation, the host drives CE# low, issues the ESR command (44H), transmits three address bytes corresponding to one of the Security Registers, and then drives CE# high. Completion of the internally timed Erase operation can be verified by polling the Busy bit in Status Register 1 or by waiting for the specified T_ESR interval.