5.21 SPI Dual Output Read with 4-Byte Address (SDOR_4Bytes)
The SPI Dual Output Read with 4-byte addressing is initiated by transmitting the 8-bit command (3CH), followed by a 4-byte address and eight dummy clock cycles. CE# must remain active-low for the duration of the SPI Dual Output Read operation. Refer to Figure 5-14 for the command sequence. Following the dummy cycles, the device outputs data on SIO[1:0], beginning at the specified address location.
Data continues streaming through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each data transfer. Once the highest memory address is reached, the Address Pointer wraps around to the beginning of the address space.