5.29 DTR Fast Read (DTR_FR)

The DTR Fast Read (DTR_FR) instruction is initiated by issuing the 8-bit command 0DH in SPI mode. After receiving the command, the device switches to dual data rate (DTR) mode to accept either a three-byte or four-byte address, followed by the required dummy clock cycles. The number of dummy clock cycles depends on the operating frequency, as specified in Table 5-7. Before executing this instruction, the appropriate dummy clock configuration must be programmed into bits [1:0] of Status Register 3. The CE# signal must remain asserted low for the entire duration of the DTR Fast Read operation. Refer to Figure 5-28 for the complete DTR Fast Read timing sequence.

After the dummy cycles, the device outputs data on SIO1/SO using dual data rate transfer, beginning at the specified address location. Data continues streaming sequentially through memory addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments and wraps to the beginning of memory after reaching the highest address.

In QPI mode, the host initiates the operation by asserting CE# low and transmitting the Read command 0DH. The device then switches to dual data rate mode for the transmission of the three-byte or four-byte address, followed by dummy clock cycles configured through the Set Read Parameters instruction (C0H), as defined in Table 5-12. The required number of dummy cycles varies according to the operating frequency. Refer to Figure 5-29 for the High-Speed Read sequence for QPI mode. Following the dummy cycles in QPI mode, the device outputs data on SIO[3:0] on the falling edge of the SCK signal, starting from the specified address location.