5.62 Read Security Register (RSR)

The Read Security Register operation is supported in both SPI and QPI modes and is used to access the three 2048-byte Security Registers. To execute a Read Security Register operation, the host drives CE# low, issues the RSR command (48H), transmits three address bytes corresponding to Security Register 1, 2, or 3, and then provides eight dummy clock cycles. Refer to Table 5-16 for the address locations of the three Security Registers.

After the dummy clock cycles, the device outputs data on the falling edge of the SCK signal, beginning at the specified address location. The data stream continues sequentially through all addresses as the internal Address Pointer automatically increments. When the highest address within the register is reached, the Address Pointer wraps around to address 0x00, which is the first byte of the register, and continues outputting data until the operation is terminated by a low-to-high transition on CE#.