5.63 Program Security Register (PSR)

The Program Security Register instruction is supported in both SPI and QPI modes and is used to program 1 to 256 bytes of data into a previously erased (FFH) Security Register 1, Security Register 2 or Security Register 3. The device ignores any Program Security Register instruction that targets an invalid or protected address. Refer to Table 5-16 for the valid Security Register address ranges. Before initiating the Program Security Register operation, the WREN instruction must be executed.

To execute a Program Security Register operation, the host drives CE# low, issues the PSR command cycle (42H), transmits three address bytes followed by the data bytes to be programmed, and then drives CE# high. The programmed data length must be between 1 and 256 bytes in whole-byte increments.

If more than 256 bytes of data are transmitted, only the last 256 bytes received are retained and programmed by the device. If the target address is not aligned to a page boundary and the transmitted data exceeds the remaining space in the page, the excess data wraps around and is programmed at the beginning of the same target page.

Completion of the internally timed Program operation can be verified by polling the Busy bit in Status Register 1 or by waiting for the specified T_PSR interval.