5.67 Write Status Register 1 (WRSR1), Write Status Register 2 (WRSR2), Write Status Register 3 (WRSR3)
The Write Status Register 1 (WRSR1), Write Status Register 2 (WRSR2) and Write Status Register 3 (WRSR3) commands are used to write new volatile or nonvolatile values into Status Register 1, Status Register 2, and Status Register 3, respectively. These commands are supported in both SPI and QPI modes.
The writable bits are:
- Status Register 1: SRP0, SEC, TB and BP[2:0]
- Status Register 2: CMP, LB[3:1], IOC and SRP1
- Status Register 3: HOLD/RST, DRV1, DRV0, DC1 and DC0
All remaining status register bits are read-only and are unaffected by Write Status Register operations. The LB[3:1] bits are nonvolatile One-Time Programmable (OTP) bits. Once set to 1, they cannot be cleared back to 0. To write nonvolatile values to the status registers, the WREN (06H) instruction must be executed before issuing a WRSR1, WRSR2 or WRSR3 command. Completion of the internally timed write operation can be verified by polling the Busy bit in Status Register 1 or by waiting for the specified TWSR interval.
To write volatile values to the status registers, a VSWREN (50H) instruction must be executed prior to issuing a WRSR1, WRSR2 or WRSR3 command. Volatile values are written within TCPH2 (30 ns). These values are lost after power‑down or following a software or hardware reset, at which point the nonvolatile status register values are restored.
To execute a WRSR1, WRSR2 or WRSR3 operation, the host drives CE# low, issues the corresponding command (01H)/(31H)/(11H) in SPI or QPI mode, followed by one data byte, and then drives CE# high. See Figure 5-54 and Figure 5-55 for the instruction sequence in SPI and QPI modes.
The IOC bit cannot be modified while the device is in QPI mode, as IOC must be set to 1 for the device to enter and remain in QPI mode.