5.23 SPI Dual I/O Read (SDIOR_4Byte)

The SPI Dual I/O Read is initiated in SPI mode by transmitting the 8-bit command (BCH). After the command phase, the device switches to dual I/O operation using SIO[1:0]. The host then transmits a 4-byte address, followed by the Set Mode configuration bits M[7:0] and the required dummy clock cycles defined in Table 5-7.

The clock cycles used for the mode configuration bits are included as part of the dummy clock count. The number of required dummy clock cycles depends on the operating frequency. Before issuing this command, the appropriate dummy clock configuration must be programmed into Status Register 3 bits [1:0]. CE# must remain active-low throughout the entire SPI Dual I/O Read operation. Refer to Figure 5-17 for the command sequence. After the dummy cycles, the device outputs data on SIO[1:0], beginning at the specified address location. Data continues streaming through successive addresses until the operation is terminated by a low-to-high transition on CE#.

The internal Address Pointer automatically increments after each transfer. When the highest memory address is reached, the Address Pointer wraps around to the beginning of the address space.

The Set Mode configuration bits M[7:0] determine whether the next instruction cycle continues as another SPI Dual I/O Read with 4-byte address operation. When M[5:4] = [1:0], the device expects the next operation to be another Read command (BCH) and does not require the opcode to be transmitted again. In this continuous read mode, the host initiates the next SDIOR_4Byte cycle by driving CE# low and transmitting the 2-bit-wide input for the 4-byte address, followed by the Set Mode configuration bits M[7:0] and the required dummy clock cycles defined in Table 5-7. After the dummy cycles, the device outputs data beginning at the specified address location. Address accesses are unrestricted.