5.28 Word Quad I/O Read (WQIOR)

The Word Quad I/O Read (WQIOR) instruction (E7H) requires the IOC bit in Status Register 2 to be set to 1 before the command is executed. The operation begins by issuing the 8-bit E7H command in SPI mode. The device then transitions to 4-bit I/O mode to receive either a three-byte or four-byte address. For this command, address bit A0 must be set to 0. After the address phase, the Set Mode configuration bits M[7:0] and dummy clock cycles are transmitted. The required number of dummy clock cycles depends on the operating frequency, as specified in Table 5-7. Before issuing this command, the appropriate dummy clock configuration must be programmed into bits [1:0] of Status Register 3. The CE# signal must remain asserted low throughout the entire Word Quad I/O Read operation. Refer to Figure 5-27 for the detailed command sequence.

Following the dummy cycles, the device outputs data on SIO[3:0], beginning at the specified address. Data continues to stream sequentially across memory addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer increments automatically and wraps to the beginning of the address space after reaching the highest memory address.

The Set Mode configuration bits M[7:0] determine whether the subsequent instruction cycle will continue as another Word Quad I/O Read operation. When M[5:4] = [1:0], the device interprets the next instruction as another E7H Read command and does not require the opcode to be retransmitted. In this mode, the host initiates the next WQIOR cycle by asserting CE# low and transmitting the 4-bit-wide address input for three or four address bytes, followed by the Set Mode configuration bits M[7:0] and the required dummy clock cycles. After the dummy cycles, the device outputs data starting from the specified address. Address access is unrestricted.

If M[5:4] is set to any value other than [1:0], the device expects the next instruction cycle to begin with a new command opcode. To exit or reset the Set Mode configuration, assert CE# low, transmit FFH on SIO0 for eight clock cycles, and then deassert CE# high.