5.10 Instructions

Instructions are used to read, write and configure the MC25VF256 device. A complete list of instructions is provided in Table 5-12. All instructions, addresses and data are transmitted with the Most Significant bit (MSb) first and the Least Significant bit (LSb).

Table 5-12. MC25VF256 Device Operation Instructions
Instruction	Description	Command Cycle⁽¹⁾	Interface		Address Cycles^(2,3)	Dummy Clocks	Data Cycles⁽³⁾	Max Frequency⁽⁴⁾
Instruction	Description	Command Cycle⁽¹⁾	SPI	QPI	Address Cycles^(2,3)	Dummy Clocks	Data Cycles⁽³⁾	Max Frequency⁽⁴⁾
Configuration
`RSTEN`	Reset Enable	66H	X	X	0	0	0	166 MHz
`RST`⁽⁵⁾	Reset Memory	99H	X	X	0	0	0	166 MHz
`EQIO`	Enable QIO	38H	X		0	0	0	166 MHz
`RSTQIO`	Reset QIO	FFH		X	0	0	0	166 MHz
Status Registers
`RDSR1`	Read Status Register 1	05H	X	X	0	0	1 to many	166 MHz
`RDSR2`	Read Status Register 2	35H	X	X	0	0	1 to many	166 MHz
`RDSR3`	Read Status Register 3	15H	X	X	0	0	1 to many	166 MHz
`REAR`	Read Extended Address Register	C8H	X	X	0	0	1	166 MHz
`WRSR1`⁽⁶⁾	Write Status Register 1	01H	X	X	0	0	1	166 MHz
`WRSR2`	Write Status Register 2	31H	X	X	0	0	1	166 MHz
`WRSR3`	Write Status Register 3	11H	X	X	0	0	1	166 MHz
`WEAR`	Write Extended Address Register	C5H or 56H	X	X	0	0	1	166 MHz
`VSWREN`	Volatile Status Register Write Enable	50H	X	X	0	0	0	166 MHz
Identification
`RMDID`	Manufacturer Device ID	90H	X	X	3 (Address value of 000000H)	0	2	166 MHz
`RMDSDIO`⁽⁷⁾	Manufacturer Device ID Dual IO	92H	X		3/4 (Address value of 00000000H)	4	2	166 MHz
`RMDSQIO`⁽⁸⁾	Manufacturer Device ID Quad IO	94H	X		3/4 (Address value of 00000000H)	6	2	166 MHz
`JEDEC ID`	JEDEC-ID Read	9FH	X	X	0	0	3	166 MHz
`SFDP`	Serial Flash Discoverable Parameters	5AH	X		3	8	1 to many	166 MHz
`SFDP`	Serial Flash Discoverable Parameters	5AH		X	3	4/6/8/10 - Configured by Set Read Parameters	1 to many	166 MHz
`RUID`	Read Unique ID	4BH	X		3/4	8	16	166 MHz
`RUID`	Read Unique ID	4BH		X	3/4	4/6/8/10 - Configured by Set Read Parameters	16	166 MHz
Read Commands with 3-Byte or 4-Byte Address Setting
`Read`	Read Memory	03H	X		3/4	0	1 to many	108 MHz
`High-Speed Read`	Read Memory at Higher Speed	0BH	X		3/4	8	1 to many	166 MHz
`High-Speed Read`	Read Memory at Higher Speed	0BH		X	3/4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`FQIOR`	Fast Quad I/O Read	EBH	X		3/4	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽⁹⁾	166 MHz
`FQIOR`	Fast Quad I/O Read	EBH		X	3/4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`WQIOR⁽⁹⁾`	Word Quad I/O Read	E7H	X		3/4	4/8 Configured by DC[1:0] bits in Status Register 3	1 to many	166 MHz
`SDOR`	SPI Dual Output Read	3BH	X		3/4	8	1 to many⁽⁷⁾	166 MHz
`SDIOR`⁽¹⁰⁾	SPI Dual I/O Read	BBH	X		3/4	4/8 Configured by DC[1:0] bits in Status Register 3	1 to many	166 MHz
`SQOR`	SPI Quad Output Read	6BH	X		3/4	8	1 to many⁽⁸⁾	166 MHz
`SQOR`	SPI Quad Output Read	6BH		X	3/4	4/6/8/10 - Configured by Set Read Parameters	1 to many	166 MHz
`DTR_FR`	DTR Fast Read	0DH	X		3/4⁽¹²⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹²⁾	108 MHz
`DTR_FR`	DTR Fast Read	0DH		X	3⁽¹²⁾	4/6/8/10 Configured by Set Read Parameters	1 to many⁽¹²⁾	108 MHz
`DTR_FDIOR`	DTR Fast Dual I/O Read	BDH	X		3/4⁽¹³⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹³⁾	108 MHz
`DTR_FQIOR`	DTR Fast Quad I/O Read	EDH	X		3⁽¹⁴⁾	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹⁴⁾	108 MHz
`DTR_FQIOR`	DTR Fast Quad I/O Read			X	3⁽¹⁴⁾	4/6/8/10 Configured by Set Read Parameters	1 to many⁽¹⁴⁾	108 MHz
`SB`	Set Burst with Wrap	77H	X		0	6	1⁽⁸⁾	166 MHz
`RBQPI`	Burst Read with Wrap in QPI	0CH		X	3/4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`DTR_RBQPI`	DTR Burst Read with Wrap in QPI	0EH		X	3/4⁽¹⁴⁾	4/6/8/10 Configured by Set Read Parameters	1 to many⁽¹⁴⁾	108 MHz
`SRP`	Set Read Parameters	C0H		X		0	1	166 MHz
Read Memory with Dedicated 4-Byte Address Commands
`Read_4Byte`	Read Data with 4-Byte Address	13H	X		4	0	1 to many	166 MHz
`High-Speed Read_4Byte`	High-Speed Read with 4-Byte Address	0CH	X		4	8	1 to many	166 MHz
`SDOR_4Byte`	SPI Dual Output Read with 4-Byte Address	3CH	X		4	8	1 to many⁽⁷⁾	166 MHz
`SDIOR_4Byte`⁽¹⁰⁾	SPI Dual I/O Read with 4-Byte Address	BCH	X		4	4/8 Configured by DC[1:0] bits in Status Register 3	1 to many	166 MHz
`SQOR_4Byte`	SPI Quad Output Read with 4 Byte Address	6CH	X		4	8	1 to many⁽⁸⁾	166 MHz
`SQOR_4Byte`	SPI Quad Output Read with 4 Byte Address	6CH		X	4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`FQIOR_4Byte`	Fast Quad I/O Read with 4-Byte Address	ECH	X		4	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽⁹⁾	166 MHz
`FQIOR_4Byte`	Fast Quad I/O Read with 4-Byte Address	ECH		X	4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`DTR_FQIOR_4Byte`	DTR Fast Quad I/O Read with 4-Byte Address	EEH	X		4	4/6/8/10 Configured by DC[1:0] bits in Status Register 3	1 to many⁽¹⁴⁾	166 MHz
`DTR_FQIOR_4Byte`	DTR Fast Quad I/O Read with 4-Byte Address	EEH		X	4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
Write Memory
`WREN`	Write Enable	06H	X	X	0	0	0	166 MHz
`WRDI`	Write Disable	04H	X	X	0	0	0	166 MHz
`WDLP`	Write Data Learning Pattern	4AH	X		0	0	1	166 MHz
`SE` ⁽¹¹⁾	4-KB Sector Erase	20H	X	X	3/4	0	0	166 MHz
`BE_32KB⁽¹¹⁾`	32-KB Block Erase	52H	X	X	3/4	0	0	166 MHz
`BE_64KB⁽¹¹⁾`	64-KB Block Erase	D8H	X	X	3/4	0	0	166 MHz
`CE`	Chip Erase	60H or C7H	X	X	0	0	0	166 MHz
`PP`	Page Program	02H	X	X	3/4	0	1 to 256	166 MHz
`SPI Quad Inp.PP (1-1-4)`	SPI Quad Input Page Program	32H	X		3/4	0	1 to 256	166 MHz
`SPI Quad PP (1-4-4)`	SPI Quad Page Program	33H or C2H	X	X	3/4	0	1 to 256	166 MHz
Write Memory with Dedicated Commands for 4-Byte of Address
`SE_4Byte`⁽¹¹⁾	4-KB Sector Erase with 4 Bytes of Address	21H	X	X	4	0	0	166 MHz
`BE_32KB_4Byte`⁽¹¹⁾	2-KB Block Erase with 4 Bytes of Address	5CH	X	X	4	0	0	166 MHz
`BE_64KB_4Byte`⁽¹¹⁾	64-KB Block Erase with 4 Bytes of Address	DCH	X	X	4	0	0	166 MHz
`PP_4Byte`	Page Program with 4 Bytes of Address	12H	X	X	4	0	1 to 256	166 MHz
`SPI Quad Inp.PP_4Byte (1-1-4)`	SPI Quad Input Page Program with 4 Bytes of Address	34H	X	X	4	0	1 to 256	166 MHz
`SPI Quad PP_4Byte (1-4-4)`	SPI Quad Page Program with 4 Bytes of Address	3EH	X	X	4	0	1 to 256	166 MHz
4-Byte Address Mode Command
`Enter_4Byte`	Enter 4-Byte Address Mode	B7H	X	X	0	0	0	166 MHz
`Exit_4Byte`	Exit 4-Byte Address Mode	E9H	X	X	0	0	0	166 MHz
Suspend/Resume
`SUS`	Program/Erase Suspend	75H	X	X	0	0	0	166 MHz
`RES`	Program/Erase Resume	7AH	X	X	0	0	0	166 MHz
Security ID
`RSR`	Read Security Register	48H	X		3/4	8	1 to many	166 MHz
`RSR`	Read Security Register	48H		X	3/4	4/6/8/10 Configured by Set Read Parameters	1 to many	166 MHz
`PSR`	Program Security Register	42H	X		3/4	0	1 to 256 bytes	166 MHz
`ESR`	Erase Security Register	44H	X		3/4	0	0	166 MHz
Power Saving
`DPD`	Enter Deep Power-Down Mode	B9H	X	X	3/4	0	0	166 MHz
`RDPD`	Release from Deep Power-Down and Read ID	ABH	X		0	0 or 24	0 or 1 to many	166 MHz
`RDPD`	Release from Deep Power-Down and Read ID	ABH		X	0	0 or 6	0 or 1 to many	166 MHz
Note: The command cycle is eight clock periods in SPI mode and two clock cycles in QPI mode. Address bits above the Most Significant bit for each density may be set to either V_IL or V_IH. Address and data cycles operate with two clock periods in QPI mode and eight clock periods in SPI mode. Unless otherwise specified, all instructions support a maximum operating frequency of 166 MHz. The `RST` command is executed only when preceded by the `RSTEN` command. Any command issued in between disables the reset operation. The Write Status Register 1 command (01h) programs both Status Register 1 and Status Register 2. Data cycles operate over four clock periods using SIO[1:0]. Data cycles operate over two clock periods and using SIO[3:0]. The IOC bit must be set to `1` before issuing this command. Address cycles, mode bits and data cycles operate over two clock periods using SIO[3:0]. The IOC bit must be set to `1` before issuing the command. Address cycles, mode bits and data cycles operate over four clock periods using SIO[1:0]. Block Erase (64 KB) uses addresses AMS–A16; Block Erase (32 KB) uses addresses AMS–A15; Sector Erase (4 KB) uses addresses AMS–A12. All remaining address bits are treated as “don’t care” and must be set to V_IL or V_IH. Address cycles are latched on both rising and falling clock edges, requiring one clock period in QPI mode and four clock periods in SPI mode. Data output is also transferred on both clock edges using the same timing. Address cycles are latched on both rising and falling clock edges, using two clock periods per address byte on SIO[1:0]. Data output is likewise transferred on both clock edges using two clock periods per data byte on SIO[1:0]. Address cycles are latched on both rising and falling clock edges using one clock period per address byte on SIO[3:0]. Data output is likewise transferred on both clock edges using one clock period per data byte on SIO[3:0].