5.33 Write Data Learning Pattern

For 6BH, EBH, 6CH, ECH, EDH and EEH instructions, a predefined Data Learning Pattern (DLP) may be used by the Flash memory controller to optimize data output timing across the four I/O pins. When DLP = 1, the device outputs the default Data Learning Pattern sequence “00110100” on each of the four I/O pins after two dummy clock cycles. During this interval, the controller can adjust and fine-tune the data sampling or latching timing for each I/O pin to achieve optimal system performance. When DLP = 0, the Data Learning Pattern output function is disabled. The Data Learning Pattern may also be programmed using the “Write Data Learning Pattern” (4AH) command in SPI mode, followed by an 8-bit user-defined pattern. This user-defined pattern is volatile and is not retained after a power cycle. Upon power-up, the Data Learning Pattern automatically returns to the default value “00110100”.