5.6 Error Correction Code (ECC)

Error Correction Code (ECC) is a commonly used technique in nonvolatile memory devices to reduce the Bit Error Rate (BER) over the device operating lifetime and improve device reliability. To support error detection and correction, redundancy data are added to store the ECC calculation results for a defined block of data.

In the MC25VF256, the internal ECC engine checks every aligned 16-byte data block stored in the memory array using the SEC-DED (Single Error Correction-Double Error Detection) Hamming code algorithm. The 16-byte ECC granularity minimizes ECC calculation latency while maintaining a high level of data integrity.

Reprogramming the same 16-byte block may trigger additional ECC calculations and result in invalid ECC information.

During read operations, the internal ECC engine checks the ECC data stored in the spare area and performs any required error correction or error detection on the data being read. The ECC status bits, SEC and DED, in the Extended Address register can be checked to determine whether ECC correction or detection occurred during the most recent read operation.

Read operations may begin at any byte address and continue across the entire memory array. Alignment to a 16-byte boundary is not required when issuing a Read command.

Additional hardware monitoring of ECC status is available through the /ECS pin, which provides real-time ECC status indication during data output. The /ECS pin can be configured to indicate either SEC (Single Error Correction) or DED (Double Error Detection) events.

By default, the /ECS pin is asserted low when an SEC event is detected. The pin behavior can be changed to indicate DED events instead by setting the ECS bit in the Extended Address register.