5.4 Hold Operation

The HOLD# pin allows active serial communication to be paused without resetting the clock sequence. When configured as a Hold pin, the RESET#/HOLD#/SIO3 pin provides this function. The HOLD# feature is disabled in QPI mode and is supported only in SPI single-bit mode and SDI dual-bit mode.

To activate Hold mode, CE# must be asserted low. Hold mode begins when the falling edge of HOLD# occurs while SCK is low. Hold mode ends when the rising edge of HOLD# occurs while SCK is low.

If the falling edge of HOLD# does not occur while SCK is low, the device enters Hold mode the next time SCK transitions to a low state. Similarly, if the rising edge of HOLD# does not occur while SCK is low, the device exits Hold mode the next time SCK reaches a low state (see Figure 5-3).

During Hold mode, the SO pin enters a high-impedance state, while the SI and SCK pins may remain at either a low (V_IL) or high (V_IH) level. CE# must remain asserted low throughout the Hold condition to preserve the device’s internal logic state.

If CE# is driven high during a Hold condition, the device’s internal logic is reset. The device remains in Hold mode as long as HOLD# stays low. To resume communication, HOLD# must be driven high and CE# must be asserted low.

Figure 5-3. Hold Operation