5.27 Fast Quad I/O Read_4Byte (FQIOR_4Byte)
The Fast Quad I/O Read with 4-byte addressing (FQIOR_4Byte) instruction
requires the IOC bit in Status Register 2 to be set to 1 before the
command is executed. In SPI mode, the operation is initiated by transmitting the 8-bit
command (ECH). The device then switches to 4-bit I/O mode for transmission of the 4-byte
address, followed by the Set Mode configuration bits M[7:0] and the required dummy clock
cycles. The clock cycles used for the mode configuration bits are included as part of
the dummy clock count. The number of required dummy clock cycles depends on the
operating frequency, as defined in Table 5-7. Before issuing this command, the appropriate dummy clock
configuration must be programmed into Status Register 3 bits [1:0]. CE# must remain
asserted low throughout the entire Fast Quad I/O Read operation. Refer to Figure 5-25 for the command sequence.
After the dummy cycles, the device outputs data on SIO[3:0], beginning at the specified address location. Data continues streaming through successive addresses until the operation is terminated by a low-to-high transition on CE#. The internal Address Pointer automatically increments after each transfer. When the highest memory address is reached, the Address Pointer wraps around to the beginning of the address space.
The Set Mode configuration bits M[7:0] determine whether the next instruction cycle continues as another Fast Quad I/O Read operation. When M[5:4] = [1:0], the device expects the next operation to be another Read command (ECH) and does not require the opcode to be transmitted again. In this continuous read mode, the host initiates the next FQIOR_4BYTE cycle by driving CE# low and transmitting the 4-bit-wide address input for the 4-byte address, followed by the Set Mode configuration bits M[7:0] and the required dummy clock cycles. After the dummy cycles, the device outputs data beginning at the specified address location. Address accesses are unrestricted.
When M[5:4] is any value other than [1:0], the device expects the next instruction initiated to be a command instruction. To reset/exit the Set Mode configuration, bring CE# low and send FFH on SIO0 for eight clocks and then bring CE# high. See Figure 5-26 for the SPI Quad I/O Mode Read sequence when M[5:4] = [1:0].
In QPI mode, the host initiates the operation by driving CE# low and transmitting the Read command (ECH), followed by four address cycles and the Set Mode configuration bits M[7:0] with the required dummy clock cycles defined by the Set Read Parameters instruction (C0H) and summarized in Table 5-12. The number of required dummy cycles depends on the operating frequency. After the dummy cycles in QPI mode, the device outputs data on SIO[3:0] on the falling edge of SCK, beginning at the specified address location.
The Set Mode configuration behavior in QPI mode is identical to SPI mode. When M[5:4] = [1:0], the device continues expecting additional Fast Quad I/O Read operations without requiring the opcode to be retransmitted. If M[5:4] contains any other value, the device expects the next instruction to begin with a command opcode.