5.22 SPI Dual I/O Read (SDIOR)
The SPI Dual I/O Read operation is initiated in SPI mode by transmitting the 8-bit command (BBH). After the command phase, the device switches to dual I/O operation using SIO[1:0]. The host then transmits three or four address bytes, followed by the Set Mode configuration bits M[7:0] and the required dummy clock cycles as defined in Table 5-7.
The clock cycles used for the mode configuration bits are included as part of the dummy clock count. The number of dummy clock cycles depends on the operating frequency. Before issuing this command, the appropriate dummy clock configuration must be programmed into Status Register 3 bits [1:0].
CE# must remain active-low throughout the entire SPI Dual Output Read operation. Refer to Figure 5-15 for the command sequence. After the dummy cycles, the device outputs data on SIO[1:0], starting from the specified address location.
The internal Address Pointer automatically increments after each transfer. When the highest memory address is reached, the Address Pointer wraps around to the beginning of the address space.
The Set Mode Configuration bits M[7:0] determine whether the next instruction cycle continues as another SPI Dual I/O Read command. When M[5:4] = [1:0], the device expects the next operation to be another Read command (BBH) and does not require the opcode to be entered again. In this mode, the host initiates the next SDIOR cycle by driving CE# low and transmitting the 2-bit-wide address input for three or four address bytes, followed by the Set Mode configuration bits M[7:0] and the required dummy clock cycles defined in Table 5-7. After the dummy cycles, the device outputs data beginning from the specified address location. Address accesses are unrestricted.
If M[5:4] contains any value other than [1:0], the device expects the next instruction to begin with a standard command opcode. To exit or reset the Set Mode configuration, the host must drive CE# low, transmit FFFFH on SIO0 over sixteen clock cycles, and then drive CE# high. Figure 5-16 illustrates the SPI Quad I/O mode read sequence when M[5:4] = [1:0].