5.25 SPI Quad Output Read_4Byte (SQOR_4Byte)

The SPI Quad Output Read with 4-byte addressing instruction (6CH) requires the IOC bit in Status Register 2 to be set to 1 before the command is executed. In SPI mode, the operation is initiated by transmitting the 8-bit command (6CH), followed by a 4-byte address and eight dummy clock cycles. CE# must remain asserted low throughout the entire SPI Quad Output Read operation. Refer to Figure 5-21 for the command sequence.

After the dummy cycles, the device outputs data on SIO[3:0], beginning at the specified address location. Data continues streaming through successive addresses until the operation is terminated by a low-to-high transition on CE#.

The internal Address Pointer automatically increments after each transfer. When the highest memory address is reached, the Address Pointer wraps around to the beginning of the address space.

In QPI mode, the host initiates the operation by driving CE# low and transmitting the Read command (6CH), followed by four address bytes and a programmable number of dummy clock cycles. The required number of dummy cycles (4, 6, 8 or 10) is configured using the Set Read Parameters instruction (C0H) and depends on the operating frequency. Refer to Figure 5-22 for the QPI High-Speed Read sequence.

After the dummy cycles in QPI mode, the device outputs data on SIO[3:0] on the falling edge of SCK, starting from the specified address location. Data continues streaming through successive addresses until terminated by a low-to-high transition on CE#.

The internal Address Pointer automatically increments after each transfer. Once the highest memory address is reached, the Address Pointer returns to address location 00000000H.