The Enable Quad I/O (EQIO) instruction (38H) places the Flash device into QPI bus mode. Before issuing the EQIO instruction, the IOC bit in Status Register 2 must be set to 1. If the IOC bit is set to 0, the EQIO instruction is ignored. Refer to Figure 5-8 for the EQIO sequence.
After the device enters QPI mode, all subsequent instructions must use 4-bit multiplexed input/output signaling until a Reset Quad I/O (RSTQIO) instruction is executed.
When transitioning to QPI mode, the device preserves the current Write Enable and Program/Erase Suspend status. However, the Wrap Length setting is reset to its default value.Figure 5-8. Enable Quad I/O Sequence (SPI)
Note: SIO[3:1] must be driven to VIH
DS20007183A
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
