5.5.1 Hardware Reset Operation

Hardware Reset is supported only in SPI mode (with IOC bit = 0). To configure the RESET#/HOLD#/SIO3 pin as a RESET# pin, the HLDRST bit in Status Register 3 must be set to 1, and the IOC bit in Status Register 2 must be set to 0.

Driving the RESET# pin high puts the device in normal operating mode. To reset the device to its initial power-on state, the RESET# pin must be driven low for a minimum duration of T_RST (approximately 1 µs). The device will require the maximum T_RECW duration to return to its initial power-on state after the RESET# pin is deasserted (driven high). Issuing a Reset during an active or suspended Program or Erase operation aborts the operation. As a result, the data within the targeted address range may be corrupted or lost. While RESET# is held low, the device does not accept any commands. The RESET# pin has the highest priority among all input signals. Hardware reset cannot release the device from Deep Power-Down or Ultra Deep Power-Down modes.