5.6.1 /ECS Output Pin
The /ECS pin provides a real-time hardware indication of ECC correction status. The pin uses an open-drain output structure. Under normal conditions, the /ECS pin remains in a high-impedance (High-Z) state. When error correction is initiated, the /ECS pin is driven low for the duration of the corresponding ECC chunk after a delay of tECSV (see Figure 5-4).
The /ECS pin is asserted low during any 16-byte read data output period in which either an SEC (Single Error Correction) or DED (Double Error Detection) event occurs. By default, the /ECS pin indicates SEC events. However, the user may configure the pin to indicate DED events instead by setting the ECS bit in the Extended Address register.
