5.5.1 Hardware Reset Operation

Hardware Reset is supported only in SPI mode when the IOC bit is set to 0. To configure the RESET#/HOLD#/SIO3 pin as a RESET# pin, set the HLDRST bit in Status Register 3 to 1 and the IOC bit in Status Register 2 to 0.

Driving the RESET# pin high places the device in normal operating mode. To reset the device to its initial power-on state, the RESET# pin must be driven low for at least the minimum T_RST duration.

After RESET# is deasserted (driven high), the device requires up to the maximum T_RECW time to return to its initial power-on state. If a reset occurs during an active or suspended Program or Erase operation, the operation is aborted, and data in the affected address range may become corrupted or lost. While RESET# is held low, the device does not accept commands. The RESET# pin has the highest priority among all input signals. Hardware reset cannot release the device from Deep Power-Down mode.