15.3.1.44 PWM Generator x I/O Control 1 Register

Note:

This bit(s) cannot be modified while PGxCON.ON = 1.
This bit(s) cannot be modified while PCLKCON.LOCK = 1. Otherwise, caution should be exercised when modifying this bit when PGxCON.ON = 1; unexpected results may occur.
This bit(s) cannot be modified while UPDATE = 1.
Caution should be exercised when modifying this bit(s) while PGxCON.ON = 1; unexpected results may occur.

Name:	APGxIOCON
Offset:	0x1440, 0x14B4, 0x1528, 0x159C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	CAPEN	CAPSRC[2:0]			CAPTREN		CAPTRSEL[1:0]
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	0	0	0		0	0


Bit	15	14	13	12	11	10	9	8
					SWAP	FORCEON	PPSEN	DTCMPSEL
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
			PMOD[1:0]		PENH	PENL	POLH	POLL
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bit 23 – CAPEN Capture Point Enable bit

Value	Description
1	CaptureTrigger Point is enabled for this register set
0	CaptureTrigger Point is not enabled for this register set

Bits 22:20 – CAPSRC[2:0] Time Base Capture Source Selection bits

Note: A capture may be initiated in software at any time by writing a ‘1’ to PGxCAP[0].

Value	Description
`111`	Reserved
`110`	Reserved
`101`	Reserved
`100`	Capture time base value at assertion of selected PCI Fault 2 signal
`011`	Capture time base value at assertion of selected PCI Current Limit signal
`010`	Capture time base value at assertion of selected PCI Feed-Forward signal
`001`	Capture time base value at assertion of selected PCI Sync signal
`000`	No hardware source selected for time base capture – software only

Bit 19 – CAPTREN Timebase Capture to Trigger Enable bit

Value	Description
`1`	Timebase capture to trigger enabled
`0`	Timebase capture to trigger disabled

Bits 17:16 – CAPTRSEL[1:0] Timebase Capture Trigger Register Selection bits

Value	Description
11	PGxTRIGF selected to store the 50% timebase captured value when enabled
10	PGxTRIGE selected to store the 50% timebase captured value when enabled
01	PGxTRIGD selected to store the 50% timebase captured value when enabled
00	PGxTRIGC selected to store the 50% timebase captured value when enabled

Bit 11 – SWAP Swap PWM Signals to PWMxH and PWMxL Device Pins bit

Value	Description
`1`	The PWMxH signal is connected to the PWMxL pin and the PWMxL signal is connected to the PWMxH pin
`0`	PWMxH/L signals are mapped to their respective pins

Bit 10 – FORCEON Force On Select bit

Value	Description
`1`	Active override happens immediately without taking the dead-time into account
`0`	Active override happens after taking the dead-time into account

Bit 9 – PPSEN Peripheral Pin Select Enable bit

Value	Description
`1`	Peripheral pin select enabled
`0`	Peripheral pin select disabled, as a result, PWM outputs are hard-mapped to pins

Bit 8 – DTCMPSEL Dead-Time Compensation Select bit

Value	Description
`1`	Dead-time compensation is controlled by PCI feed-forward limit logic
`0`	Dead-time compensation is controlled by PCI Sync logic

Bits 5:4 – PMOD[1:0] PWM Generator Output Mode Selection bits

Value	Description
`11`	Reserved
`10`	PWM Generator outputs operate in Push-Pull mode
`01`	PWM Generator outputs operate in Independent mode
`00`	PWM Generator outputs operate in Complementary mode

Bit 3 – PENH PWMxH Output Port Enable bit

Value	Description
`1`	PWM Generator controls the PWMxH output pin
`0`	PWM Generator does not control the PWMxH output pin

Bit 2 – PENL PWMxL Output Port Enable bit⁽²⁾

Value	Description
`1`	PWM Generator controls the PWMxL output pin
`0`	PWM Generator does not control the PWMxL output pin

Bit 1 – POLH PWMxH Output Polarity bit

Value	Description
`1`	Output pin is active-low
`0`	Output pin is active-high

Bit 0 – POLL PWMxL Output Polarity bit

Value	Description
`1`	Output pin is active-low
`0`	Output pin is active-high

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