15.3.1.32 PWM Clock Control Register
Legend: C = Clearable bit
| Name: | APCLKCON |
| Offset: | 0x1400 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVSEL[1:0] | Reserved | MCLKSEL | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 8 – LOCK Lock bit
| Value | Description |
|---|---|
1 |
Write-protected registers and bits are locked. |
0 |
Write-protected registers and bits are unlocked. |
Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection bits
| Value | Description |
|---|---|
11 |
Divide ratio is 1:16. |
10 |
Divide ratio is 1:8. |
01 |
Divide ratio is 1:4. |
00 |
Divide ratio is 1:2. |
Bit 2 – Reserved
Maintain as ‘1’
Bit 0 – MCLKSEL PWM Master Clock Selection bit
Note: Do not change the
MCLKSEL[1:0] bits while ON (PGxCON[15]) =
1.| Value | Description |
|---|---|
| 1 | CKLGEN5 |
| 0 | UPB clock |